changes
This commit is contained in:
Miguel Fuertes committed
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8f182fa02e
commit
78f2b0f688
1 file changed
+86
-70
@@ -2,7 +2,8 @@
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/*
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* DRM driver for Sitronix ST7735S display panels
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*
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* Based on st7735r driver by David Lechner
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* Based on st7735r driver by David Lechner <david@lechnology.com>
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* Android DTS sequence implementation
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*/
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#include <linux/backlight.h>
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@@ -53,6 +54,10 @@ struct st7735s_priv {
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const struct st7735s_cfg *cfg;
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};
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/*
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* Android DTS initialization sequence from MSM8916
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* DO NOT modify order or add extra commands
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*/
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static void st7735s_pipe_enable(struct drm_simple_display_pipe *pipe,
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struct drm_crtc_state *crtc_state,
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struct drm_plane_state *plane_state)
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@@ -62,97 +67,106 @@ static void st7735s_pipe_enable(struct drm_simple_display_pipe *pipe,
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dbidev);
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struct mipi_dbi *dbi = &dbidev->dbi;
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int ret, idx;
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u8 addr_mode;
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if (!drm_dev_enter(pipe->crtc.dev, &idx))
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return;
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DRM_DEBUG_KMS("\n");
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pr_info("st7735s: === BEGIN ANDROID SEQUENCE ===\n");
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ret = mipi_dbi_poweron_reset(dbidev);
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if (ret)
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if (ret) {
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pr_err("st7735s: poweron_reset failed: %d\n", ret);
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goto out_exit;
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/* Secuencia de inicialización basada en Android DTS */
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/* Frame rate control - normal mode */
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mipi_dbi_command(dbi, ST7735S_FRMCTR1, 0x05, 0x3c, 0x3c);
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/* Frame rate control - idle mode */
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mipi_dbi_command(dbi, ST7735S_FRMCTR2, 0x05, 0x3c, 0x3c);
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/* Frame rate control - partial mode */
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mipi_dbi_command(dbi, ST7735S_FRMCTR3, 0x05, 0x3c, 0x3c,
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0x05, 0x3c, 0x3c);
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/* Display inversion control */
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mipi_dbi_command(dbi, ST7735S_INVCTR, 0x03);
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/* Power control */
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mipi_dbi_command(dbi, ST7735S_PWCTR1, 0x0e, 0x0e, 0x04);
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mipi_dbi_command(dbi, ST7735S_PWCTR2, 0xc0);
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mipi_dbi_command(dbi, ST7735S_PWCTR3, 0x0d, 0x00);
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mipi_dbi_command(dbi, ST7735S_PWCTR4, 0x8d, 0x2a);
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mipi_dbi_command(dbi, ST7735S_PWCTR5, 0x8d, 0xee);
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/* VCOM control */
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mipi_dbi_command(dbi, ST7735S_VMCTR1, 0x0c);
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/* Memory access control - adaptado según rotación */
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switch (dbidev->rotation) {
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default:
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addr_mode = ST7735S_MX | ST7735S_MY;
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break;
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case 90:
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addr_mode = ST7735S_MX | ST7735S_MV;
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break;
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case 180:
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addr_mode = 0;
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break;
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case 270:
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addr_mode = ST7735S_MY | ST7735S_MV;
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break;
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}
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if (priv->cfg->rgb)
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addr_mode |= ST7735S_RGB;
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/* 1. EXIT_SLEEP_MODE (0x11) - delay 150ms (0x96) */
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pr_info("st7735s: [1/19] EXIT_SLEEP_MODE (0x11)\n");
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mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
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msleep(150);
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mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
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/* 2. SET_ADDRESS_MODE (0x36) - 0x00 */
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pr_info("st7735s: [2/19] SET_ADDRESS_MODE (0x36) = 0x00\n");
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mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
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/* Display inversion ON (0x21 del DTS Android) */
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mipi_dbi_command(dbi, MIPI_DCS_ENTER_INVERT_MODE);
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/* 3. SET_COLUMN_ADDRESS (0x2a) - 0,0,0,131 */
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pr_info("st7735s: [3/19] SET_COLUMN_ADDRESS (0x2a) = 0,0,0,131\n");
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mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS,
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0x00, 0x00, 0x00, 0x83);
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/* Positive gamma correction */
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/* 4. SET_PAGE_ADDRESS (0x2b) - 0,0,0,131 */
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pr_info("st7735s: [4/19] SET_PAGE_ADDRESS (0x2b) = 0,0,0,131\n");
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mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS,
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0x00, 0x00, 0x00, 0x83);
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/* 5. SET_PIXEL_FORMAT (0x3a) - 0x05 (16-bit RGB565) */
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pr_info("st7735s: [5/19] SET_PIXEL_FORMAT (0x3a) = 0x05\n");
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mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, 0x05);
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/* 6. FRMCTR1 (0xb1) - 0x05,0x3c,0x3c */
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pr_info("st7735s: [6/19] FRMCTR1 (0xb1)\n");
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mipi_dbi_command(dbi, ST7735S_FRMCTR1, 0x05, 0x3c, 0x3c);
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/* 7. FRMCTR2 (0xb2) - 0x05,0x3c,0x3c */
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pr_info("st7735s: [7/19] FRMCTR2 (0xb2)\n");
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mipi_dbi_command(dbi, ST7735S_FRMCTR2, 0x05, 0x3c, 0x3c);
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/* 8. FRMCTR3 (0xb3) - 0x05,0x3c,0x3c,0x05,0x3c,0x3c */
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pr_info("st7735s: [8/19] FRMCTR3 (0xb3)\n");
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mipi_dbi_command(dbi, ST7735S_FRMCTR3, 0x05, 0x3c, 0x3c,
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0x05, 0x3c, 0x3c);
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/* 9. INVCTR (0xb4) - 0x03 */
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pr_info("st7735s: [9/19] INVCTR (0xb4) = 0x03\n");
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mipi_dbi_command(dbi, ST7735S_INVCTR, 0x03);
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/* 10. PWCTR1 (0xc0) - 0x0e,0x0e,0x04 */
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pr_info("st7735s: [10/19] PWCTR1 (0xc0)\n");
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mipi_dbi_command(dbi, ST7735S_PWCTR1, 0x0e, 0x0e, 0x04);
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/* 11. PWCTR2 (0xc1) - 0xc0 */
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pr_info("st7735s: [11/19] PWCTR2 (0xc1) = 0xc0\n");
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mipi_dbi_command(dbi, ST7735S_PWCTR2, 0xc0);
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/* 12. PWCTR3 (0xc2) - 0x0d,0x00 */
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pr_info("st7735s: [12/19] PWCTR3 (0xc2)\n");
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mipi_dbi_command(dbi, ST7735S_PWCTR3, 0x0d, 0x00);
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/* 13. PWCTR4 (0xc3) - 0x8d,0x2a */
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pr_info("st7735s: [13/19] PWCTR4 (0xc3)\n");
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mipi_dbi_command(dbi, ST7735S_PWCTR4, 0x8d, 0x2a);
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/* 14. PWCTR5 (0xc4) - 0x8d,0xee */
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pr_info("st7735s: [14/19] PWCTR5 (0xc4)\n");
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mipi_dbi_command(dbi, ST7735S_PWCTR5, 0x8d, 0xee);
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/* 15. VMCTR1 (0xc5) - 0x0c */
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pr_info("st7735s: [15/19] VMCTR1 (0xc5) = 0x0c\n");
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mipi_dbi_command(dbi, ST7735S_VMCTR1, 0x0c);
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/* 16. GAMCTRP1 (0xe0) - Positive Gamma */
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pr_info("st7735s: [16/19] GAMCTRP1 (0xe0)\n");
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mipi_dbi_command(dbi, ST7735S_GAMCTRP1,
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0x0c, 0x1c, 0x0f, 0x18, 0x36, 0x2f, 0x27, 0x2a,
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0x27, 0x25, 0x2d, 0x3c, 0x00, 0x05, 0x03, 0x10);
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/* Negative gamma correction */
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/* 17. GAMCTRN1 (0xe1) - Negative Gamma */
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pr_info("st7735s: [17/19] GAMCTRN1 (0xe1)\n");
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mipi_dbi_command(dbi, ST7735S_GAMCTRN1,
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0x0c, 0x1a, 0x09, 0x09, 0x26, 0x22, 0x1e, 0x25,
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0x25, 0x25, 0x2e, 0x3b, 0x00, 0x05, 0x03, 0x10);
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/* Pixel format: 16-bit color (0x3a 0x05 = RGB565) */
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mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT,
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MIPI_DCS_PIXEL_FMT_16BIT);
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/* 18. ENTER_INVERT_MODE (0x21) */
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pr_info("st7735s: [18/19] ENTER_INVERT_MODE (0x21)\n");
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mipi_dbi_command(dbi, MIPI_DCS_ENTER_INVERT_MODE);
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/* Column address set */
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mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS,
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0x00, 0x00, 0x00, 0x83);
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/* Row address set */
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mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS,
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0x00, 0x00, 0x00, 0x83);
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/* Exit sleep mode */
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mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
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msleep(120);
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/* Display on */
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/* 19. SET_DISPLAY_ON (0x29) - delay 120ms (0x78) */
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pr_info("st7735s: [19/19] SET_DISPLAY_ON (0x29)\n");
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mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
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msleep(120);
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pr_info("st7735s: === SEQUENCE COMPLETE, calling flush ===\n");
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mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
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pr_info("st7735s: === FLUSH COMPLETE ===\n");
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out_exit:
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drm_dev_exit(idx);
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@@ -162,15 +176,17 @@ static const struct drm_simple_display_pipe_funcs st7735s_pipe_funcs = {
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DRM_MIPI_DBI_SIMPLE_DISPLAY_PIPE_FUNCS(st7735s_pipe_enable),
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};
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/* Configuración para panel 132x132 (128x128 área visible) */
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static const struct st7735s_cfg st7735s_128x128_cfg = {
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.mode = { DRM_SIMPLE_MODE(128, 128, 22, 22) },
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.left_offset = 2,
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.top_offset = 1,
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.write_only = false,
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.rgb = false, /* BGR order por defecto */
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.rgb = false,
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};
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/* ... resto del driver igual ... */
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DEFINE_DRM_GEM_DMA_FOPS(st7735s_fops);
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static const struct drm_driver st7735s_driver = {
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